caching - How to divide the L2 cache between the cores on a ARM Cortex-A7? -

context , goal

i'd run 2 standalone applications on olimex a20 lime platform run arm cortex-a7. goal dedicate 1 core each application. far good.

now i'd divide l2 cache between cores in following manner:

       l2 cache (256kb) --------------------------- |    cpu0    |    cpu1    | |   (128kb)  |   (128kb)  | --------------------------- 

therefore, each core have access his private 128kb of l2 cache.

question

how can divide l2 cache between cores on arm cortex-a7?

from understanding, on previous soc, external cache controller pl310 used. now, newer soc cortex-a15 , cortex-a7 uses integrated cache controller. controller somehow integrated scu component.

i've found in cp15 system registers related cache csselr, ccsidr, clidr, etc., system control register (sctlr). none of them seems let me configure size each core. still possible do?

thanks help.

edit

here, standalone application mean in fact linux os. goal dedicate 1 core 1 os. therefore each os runs on (see) monoprocessor system underneath. whole framework running, far good.

thanks answers i've received, understand should ok cores both use l2 if standalone os not using same virtual mapping. it's indeed same 2 processes having own virtual address space.

however last thing bothers me security aspect:

if both cores share whole l2 cache, is technically possible 1 core access cached data of other core?

references

• arm cortex-a7 mpcore trm
  • about l2 memory system (7.1)
  • identification registers (4.2.18)

two pieces of code don't use same physical memory not cause cache conflicts, cache physically tagged on a7 processors (any arm processor virtualization extensions).

on a7, cache lines vm id tagged. if want enforce separation between codes running on 2 cores setup second stage pagetable each core , mark them different vm id's. violation of address space el0/1 cause trap el2 (hypervisor). similar how el1 enforces separation of el0 address spaces.

to configure have have access bootcode. secure el1/el3 bootcode directly switches non-secure el1 mode. have modify flow , switch el2 mode instead. while in el2 mode setup , enable non-intersecting 2nd stage page table each core. setup el2 vector table catch 2nd stage mmu exceptions.

this result in minor drop in performance. more efficient using kvm (last time checked kvm not suited arm v7 , causes lot of overheads due design). xen more suited arm, require lot of setup side.

if not planning use virtualization extensions/ 2nd stage page tables / smp; turn off actlr.smp bit. might give bit of boost in performance l1 cache concurrency blocks turned off.

note: answer edited question