vhdl - Logic synthesis from an arbitary piece of code -

i have completed on project making physical logic gates , looking way turn arbitrary program series of logic gates can use them.

i need program can take arbitrary function (say f= x^2 -1) directly series of logic gates. exist?

i have found verilog , several other open source options not appear output circuit diagrams. there quartus ii , other programs convert vhdl code schematic.

preferably compiles python/c++ logic gate schematic directly - language fine.

thanks.

edit: mean physical gates - use ball bearings!

i have of 1-bit-input/1-bit-output gates , of 2-bit-input/1-bit output-gates. these can construct maj gate error correction.

write arbitrary code in vhdl, turning vhdl gates synthesis tool does.

not write synthesisable; file handling can't translated gates, neither can conventionally uses heap (such malloc, or pointers, in c, or "new" , access types in vhdl). floating point can synthesised (with vhdl-2008) it's not quite simple signal : real; <= 2.0 * x * x - 1.0; have use types synthesisable floating point library. there may negotiation tool programming language subset can use.

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but i'm sensing different question here : how translate arbitrary code my logic gates, implemented in (technology not described in question). , that's harder answer.

synthesis tools come vendor such fpga vendor, , translate arbitrary code that vendor's logic gates, not yours.

the ideal solution create library describing logic technology, plugs vendor-neutral synthesis tool, such synplicity synopsys. synplicity can synthesise technology instead of fpga vendor's.

ok, creating library task on par writing backend custom cpu's instruction set, , integrating backend gcc. except synplicity, unlike gcc, isn't open source, without considerable financial , technical resources, , , internal documentation major eda tool company, it's approximately impossible. (at point i'd delighted corrected who's done it)

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so need different approach.

back fpga synth tools : i'll use xilinx xst example. it'll synth xilinx primitives, in xilinx closed internal format.

however there's option labelled "write post-synthesis netlist".

using that, can structural vhdl file representing translation of arbitrary code xilinx gates, flip-flops, , other elements, drawn simprims library.

attempt compile (e.g. in simulator) without making simprims library visible (e.g. library simprims; use simprims; statements commented out , you'll valuable:

a list of compilation errors

not valuable, may think : except it's list of gates, flipflops , other elements needed implement design.

if can find (or create) one-to-one correspondence between these, , elements in chosen technology, can map netlist technology.

if there simprims elements don't have equivalents, need implement them - e.g. creating 3-input , gates networks of 2-input nand gates have.

use corresponding elements own (vhdl) library, instead of simprims, , should, in theory, have usable compiled design.

(you're on own problems layout, routing, timing analysis. not trivial, sake of question i'm assuming "project making physical gates" has these covered...)